1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and particularly, to a configuration for reducing a time required for data writing/reading in a non-volatile semiconductor memory device. Specifically, the present invention relates to an array configuration for and an accessing scheme for fast accessing of a non-volatile semiconductor memory device containing a variable resistance element, such as a magneto-resistance element or a phase change element, as a storage element.
2. Description of the Background Art
Among semiconductor memory devices that store data in a non-volatile manner, there is included a magnetic semiconductor memory device (MRAM: Magnetic Random Access Memory) that utilizes a tunnel junction (MTJ: Magnetic Tunnel Junction) structure exhibiting a tunneling magneto-resistance (TMR) effect as a storage element.
In a TMR element (or an MTJ element), a storage element is structured by two magnetic layers with an insulating layer (a tunneling barrier layer) interposed in between. Normally, one of the two magnetic layers is formed with an antiferromagnetic layer having its magnetization direction fixed, and the other magnetic layer has its magnetization direction changed in accordance with write data. Depending on the relationship between the magnetization directions of the fixed layer having the fixed magnetization direction and of the free layer having the magnetization direction changed in accordance with write data, the tunneling resistance of the tunneling barrier film changes due to magneto-resistance effect. Specifically, the magneto-resistance becomes the lowest when the magnetization directions of the free layer and the fixed layer are parallel, and the magneto-resistance becomes the highest when the magnetization directions of the free layer and the fixed layer are anti-parallel or opposite. These magneto-resistance values are correlated with “1” and “0” of storage data. As data is stored by the magnetization direction and the magnetization direction is retained until a magnetic field is newly applied externally, data can be stored in a non-volatile manner.
As an amount of current flowing through the TMR element changes in accordance with a magneto-resistance value, data reading is performed by determining storage data in accordance with the magnitude of the current value.
An exemplary configuration of such a magnetic semiconductor memory device is shown in Prior Art Reference 1 (Japanese Patent Laying-Open No. 2003-249629).
In the configuration shown in Prior Art Reference 1, storage elements formed of magneto-resistance elements such as TMR elements are arranged in rows and columns, and one read block is constructed by a prescribed number of memory cells. In the read block, first ends of the TMR elements are individually connected to respective bit lines, and the opposite second ends of the TMR elements are coupled to a source line via a common read select switch. Prior Art Reference 1 intends to reduce the occupying area of the memory cells by connecting one read select switch to a plurality of TMR elements, as compared to the configuration where a select transistor is arranged for each memory cell. Additionally, in data reading, it is intended to achieve fast data reading, by selectively driving a bit line and a read select switch so that a read current is caused to flow through only one memory cell.
In the configuration shown in Prior Art Reference 1, in one read block, TMR elements are respectively connected to different read bit lines, and a source line is commonly connected to the read blocks aligned in a direction perpendicular to the read bit lines. To one read block, one read select gate is connected, and a plurality of TMR elements in one read block are connected commonly to a source line. With this configuration, it is intended to read storage data of TMR elements in the read block in parallel simultaneously.
However, when a source line is provided commonly to a plurality of read blocks and the interconnection resistance of the source line is large, such a problem occurs that a read current (memory cell current) from a selected memory cell (TMR element) flows to raise the source line potential (in data reading, the source line is coupled to the ground potential), the read current cannot be sufficiently supplied, and fast data reading cannot be achieved. Further, due to the raised source line potential, the memory cell current may be limited and correct data reading may not be performed.
In order to reduce the resistance of the source line, the following approach may be considered. That is, a source line is formed of, for example, an N type impurity layer and a low resistance layer such as cobalt silicide (CoSi) layer is formed on the surface of the source impurity layer, to achieve the reduction in the resistance of the source line contact and the interconnection resistance of the source line. However, with such a configuration, it is still inadequate to obtain a correct read current, due to the interconnection resistance and the distribution of the source potential (floating-up) over the entire source line as the source line is arranged extending along a plurality of read blocks and thus the interconnection length is large.
Further, in the configuration shown in Prior Art Reference 1, a write word line driven to a selected state in data writing and a read bit line driving a memory cell current in data reading are formed of a common interconnection line. With the common configuration of the write word line and read bit line, it is intended to simplify the array configuration. Accordingly, a read bit line cannot be used in data writing, and conversely, a write word line cannot be used in data reading. Thus, it is allowed to alternatively perform data writing and data reading, and it is not allowed to implement an operation mode performing writing and reading in parallel, such as read-modify-write mode in which write data is changed by read data.
Still further, in the configuration shown in Prior Art Reference 1, a read bit line is connected to an internal data line that is connected to a read sense amplifier. From a read circuit including the read sense amplifier, a read current is supplied to a selected read bit line. As the write word line and the read bit line are formed into a common line, a write word line driver and the read sense amplifier are both connected to the internal data line. Accordingly, there are problems that the load of the internal data line is large, the read current cannot be driven fast in data reading, and fast accessing cannot be achieved. Particularly, in data reading, the internal data line, to which the sense amplifier is connected, is directly driven by a memory cell current, and the memory cell current is required to drive the internal data line with a large load. Therefore, there is a problem that fast reading cannot be achieved.